1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various novel methods of forming replacement gate structures on transistor devices and the resulting novel device structures.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Field Effect Transistors (“FETs”) come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, vertical transistors, nanowire devices, etc.
A conventional planar FET is a planar device wherein the entire channel region of the device is formed parallel and slightly below the planar upper surface of the semiconducting substrate. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 wherein the fins 14 of the device 10 are made of the material of the substrate 12, e.g., silicon. The device 10 includes a plurality of fin-formation trenches 13, three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. The spacer 18 is typically made of silicon nitride, but in some cases it may be made of a material having a lower dielectric constant (k) than that of silicon nitride. An insulating material 17, e.g., silicon dioxide, provides electrical isolation between the fins 14. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the gate length of the device, i.e., the direction of current travel in the device 10 when it is operational. The gate width of the device 10 is orthogonal to the gate length direction. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. The portions of the fins 14 that are positioned outside of the spacers 18 will become part of the source/drain regions of the device 10.
For many FET devices, the gate structures are initially formed as continuous line-type structures that extend across the entire substrate, including across both active regions and isolation regions. In advanced integrated circuit (IC) products, the gate structures for the transistor devices are typically manufactured using the well-known replacement gate (or “gate-last”) manufacturing technique. In general, the replacement gate manufacturing technique involves the formation of a sacrificial (or “dummy”) gate structure comprised of a sacrificial gate insulation layer (e.g., silicon dioxide) and a layer of a sacrificial gate electrode material (e.g., polysilicon or amorphous silicon). Various process operations are performed with the sacrificial gate structure in position, e.g., source/drain implantation processes, the formation of epi semiconductor material in the source/drain regions of the transistor devices, etc. At some point in the manufacturing process, the sacrificial gate structure will be removed to define a replacement gate cavity. Thereafter, materials for the replacement gate structure will be formed in the replacement gate cavity and a final gate cap will be formed over the replacement gate structure. In advanced devices, such a replacement gate structure may comprise a high-k (k value of 10 or greater) gate insulation layer and one or more metal-containing layers of material that collectively function as the conductive gate electrode for the replacement gate structure.
For many FET devices, the initial sacrificial gate structures are initially formed as continuous line-type structures that extend across the entire substrate, including across both active regions and isolation regions. The long continuous line-type sacrificial gate structures are formed by depositing the materials for the sacrificial gate structures across the entire substrate, forming a patterned gate etch mask above the deposited sacrificial gate materials and performing one or more etching processes through the patterned gate etch mask to remove the exposed portions of the sacrificial gate materials. At that point, a spacer structure will be formed adjacent the long continuous line-type sacrificial gate structures. As noted above, at some point after other processing has occurred, e.g., after formation of epi material in the source/drain regions of the devices, portions of the long continuous line-type sacrificial gate structures will be removed or “cut” so as to define individual portions or segments of the original long continuous line-type sacrificial gate structures which will eventually be removed and replaced with final replacement gate structures. After the cutting process is completed, there is “gate-cut” opening or space between the two cut end surfaces of the now-separated first and second sacrificial gate structures. This may sometimes be referred to as “tip-to-tip” spacing between the individual sacrificial gate structures. The gate-cut opening located between the cut end surfaces of the sacrificial gate structures is typically filled with an insulation material.
As device dimensions continue to decrease and as packing densities of transistor devices on a substrate continue to increase, various problems have arisen as it relates to manufacturing replacement gate structures on transistor devices. More specifically, as device scaling continues, the vertical height of the sacrificial gate structures has increased, while the lateral width (i.e., gate length or critical dimension) of the sacrificial gate structures has decreased. As a result, the aspect ratio (height/lateral width) has increased, thereby making the cutting of the original long continuous line-type sacrificial gate structures into individual sacrificial gate structure segments more problematic. For example, given the increased aspect ratio of the sacrificial gate structures on more advanced devices, the act of cutting the original long continuous line-type sacrificial gate structures may be incomplete in that undesirable residual amounts of the sacrificial gate material may remain in place after the cutting process is completed. The presence of such undesirable residual materials from the sacrificial gate structures may make the formation of quality replacement gate structures more difficult and, in some cases, constitute a conductive pathway between the final replacement gate structures that will be formed for the transistor devices. That is, residual conductive materials of the sacrificial gate structure that remains positioned at the bottom of the gate-cut opening may constitute an electrical short between the two final replacement gate structures when they are formed on the IC product, which may thereby result in decreased device performance and/or complete device failure.
The present disclosure is directed to various novel methods of forming replacement gate structures on transistor devices and the resulting novel device structures that may eliminate or at least reduce one or more of the problems identified above.